1. Field of the Invention
The present invention relates to a method of etching a silicon nitride layer and a method of manufacturing a semiconductor device including a step of patterning the silicon nitride layer.
2. Description of the Prior Art
With the development of miniaturization of the semiconductor integrated circuit (LSI), a SAC (Self Alignment Contact) technique and a BLC (Border Less Contact) technique have been employed to arrange the wirings from an impurity diffusion layer to a field insulating film.
According to the SAC technique, in the event that wirings are connected to two MOS transistors which employ one impurity diffusion layer as a common constituent element and the wirings are to be connected to a common impurity diffusion layer between two gate electrodes, connecting positions of the wirings are regulated by an insulating layer formed on surfaces of two gate electrodes.
Like the above, with the use of the SAC technique, the wirings can be easily and firmly connected to the impurity diffusion layer between the gate electrodes which are narrowed together with the miniaturization.
According to the BLC technique, grooves are formed in a device isolation region of a semiconductor substrate, then silicon oxide is filled in the grooves, then an impurity diffusion layer is formed on a semiconductor substrate, then wirings are formed in a region spreading from the impurity diffusion layer to the device isolation region.
If such BLC technique is employed, an alignment margin in the contact area between the wiring and the impurity diffusion layer can be increased.
Next, examples of the semiconductor device employing the SAC technique and the BLC technique in the prior art will be explained hereunder.
SAC technique
As shown in FIG. 17A, a gate electrode 103 is formed on a silicon substrate 100 via a gate insulating layer 102 and then a cap layer 104 made of SiO2 is formed on the gate electrode 103. Side walls 105 made of SiO2 are formed on the side surfaces of the gate electrode 103. Impurity diffusion layers 101 on the silicon substrate 100 are formed by a first ion implantation with low concentration after the gate electrodes 103 have been formed and a second ion implantation with high concentration after the side walls 105 are formed to have an LDD (Lightly Doped Drain) structure.
In such condition, after a thin protection film 106 made of SiO2 is formed on an overall surface, a covering layer 107 made of Si3N4 is formed and then an interlayer insulating layer 108 made of BPSG and an intermediate layer 109 made of SiO2 are formed on the covering layer 107.
Subsequently, in order to form contact holes in the interlayer insulating layer 108 and the intermediate layer 109, a photoresist 110 having windows 111 over gaps between the side walls 105 is formed.
In turn, as shown in FIG. 17B, contact holes 112 are formed by dry-etching the interlayer insulating layer 108 via the windows 111 of the photoresist 110 in the vertical direction. In this case, the covering layer 107 made of Si3N4 having a small etching rate may be used as an etchant to etch the interlayer insulating layer 108 and the intermediate layer 109. Hence, the cap layer 104 and the side walls 105 still remain beneath the covering layer 107 because the covering layer 107 serves as an etching stopper.
Next, as shown in FIG. 17C, the covering layer 107 and the protection film 106 formed beneath the contact holes 112 are removed by etching. Thus, the impurity diffusion layers 101 are formed on the side surfaces of the side walls 105 are exposed. As the method of etching the covering layer 107 made of Si3N4, reactive ion etching using the fluorine gas can be employed. In addition, etching of the protection film 106 made of SiO2 is executed by use of dilution hydrogen fluoride.
After the photoresist 110 has been removed, wirings are formed on the interlayer insulating layer 108, though not particularly depicted, and then the wirings are connected to the impurity diffusion layers 101 via clearances between the contact holes 112 and clearances between the side walls 105.
BLC technique
First, steps of forming up to a structure shown in FIG. 18A will be explained.
A groove 112 is formed is formed in the device isolation region of the silicon substrate 121, and then a buried insulating film 123 made of silicon oxide is filled into the groove 122. As a method of filling the buried insulating film 123 into the groove 122, such a method can be employed, for example, that the buried insulating film 123 is formed by CVD (Chemical Vapor Deposition) in the groove 122 and on the silicon substrate 121 and then the buried insulating film 123 on a surface of the silicon substrate 121 is removed by polishing.
A gate insulating film 124, a gate electrode 125, and a gate covering insulating film 126 are then formed in an active region. Then, low-impurity concentration regions 127a, 127d are formed by ion-implanting the impurity into the silicon substrate 121 on both sides of the gate electrode 125 at a low dosage by use of the gate electrode 125 as a mask.
Then, an insulating film 128 made of silicon nitride and silicon nitride oxide is formed on the silicon substrate 121, the gate covering insulating film 126, and the low-impurity concentration regions 127a, 127d.
Thereafter, as shown in FIG. 18B, the insulating film 128 is etched in the substantially vertical direction by RIE (Reactive Ion Etching) such that the insulating film 128 remains on side surfaces of the gate electrode 125 and the gate covering insulating film 126. Such insulating films 128 remaining on the side surfaces of the gate electrode 125 are called side walls.
Then, as shown in FIG. 18C, using the side walls 128 and the gate covering insulating film 126 as a mask, impurity is ion-implanted at a high dosage into the active region which is not covered with the gate electrode 125 and the side walls 128. Therefore, high-impurity concentration regions 129a, 129d are formed in the active region.
The LDD structure impurity diffusion layers 129a, 129d can be formed on both sides of the gate electrode 125 by the high-impurity concentration regions 129s, 129d and the low-impurity concentration regions 127a, 127d.
As shown in FIG. 18D, silicide layers 131s, 131d are formed on surfaces of the low-impurity concentration regions 127s, 127d by the salicide (self-align silicide) technique.
Thus, a MOS transistor can be formed in the active region.
After this, as shown in FIG. 18E, a silicon nitride film 132 is formed in the active region and the device isolation region, and then an interlayer insulating film 133 made of silicon oxide is formed on the silicon nitride film 132.
Then, a plurality of contact holes 134a, 134d are formed in the silicon nitride film 132 and the interlayer insulating film 133 by the photolithography technique. These contact holes 134s, 134d are formed on two silicide layers 131s, 131d in the active region. In this case, if miniaturization of the semiconductor device is considered, a diameter of the contact holes 134s, 134d cannot be formed to have a wide margin in size rather than the high-impurity concentration regions 129s, 129d and as a result the contact holes 134s, 134d can be formed to cross over the buried insulating film 123.
Then, the wirings (not shown) are provided to the LDD structure impurity diffusion layers 129s, 129d via the contact holes 124s, 134d.
With the above, the common SAC technique and the common BCL technique have been described.
Meanwhile, for example, as set forth in Patent Application Publication (KOKAI) 6-12765, it has been deduced that an etching rate of Si3N4 can be enhanced rather than that of Si if one of CH2F2 and CH3F is employed as an etching gas to etch a covering layer made of silicon nitride, and that the etching rate of Si3N4 can be enhanced up to about ten times those of SiO2 and Si if the flow rate of the gas is changed and the pressure is set higher.
In general, if Si3N4 is etched by use of a gas mixture which consists of a fluorine compound gas as a major gas such as CF4, SF6, or NF3, oxygen, etc., following etching performance has been derived.Si etching rate>Si3N4 etching rate>SiO2 etching rate
In this case, a value α/β obtained by dividing the etching rate α of Si3N4 by the etching rate β of SiO2 (referred to as an “etching selectivity of Si3N4 to SiO2” hereinafter) has been 2 to 3. Therefore, such gas mixture can be used for the SAC and the BLC, but such gas mixture enables only isotropic etching. Besides, damage of the silicon substrate is increased under such SiNx etching condition.
According to the inventors' experiment using another etching gas which includes CF4 and CHF3 mainly, following etching performance has been derived.SiO2 etching rate>Si3N4 etching rate>Si etching rate
In this case, the etching selectivity of Si3N4 to SiO2 has been in the range of 0.5 to 1 and such another etching gas enables anisotropic etching. Such another etching gas can be used for information of the contact hole and removal of the LOCOS nitride film.
Meanwhile, followings have arisen as problems in the SAC technique.
If the fluorine gas is used as the etching gas, the etching selectivity of Si3N4 to SiO2 or Si has been enhanced, but such fluorine gas has enabled only isotropic etching. Hence, a patterning accuracy of the silicon nitride layer has been degraded.
For instance, as shown in FIG. 17A, if etching isotropy is enhanced on the etching step of the covering layer 107, the covering layer 107 is side-etched and further extended from the contact hole 112 laterally. As a result, recesses are formed between the cap layer 104 and the interlayer insulating layer 108 along the lateral direction. If such lateral recesses are considerably deep, i.e., an amount of the side etching becomes large, the covering layer 107 has been eliminated over the gate electrodes 103 so that the lateral holes are formed. Such lateral holes would cause short-circuit of two wirings passing through the neighboring contact holes 112.
On the contrary, it may be considered that an etching time can be shortened in order to prevent the side etching of the covering layer 107. However, in this case, because of insufficient etching, the covering layer 107 has remained on the side surfaces of the side walls 105. Thus, respective areas of the impurity diffusion layers 101 which are exposed on the side of the side walls 105 are made small. Under such condition, a contact resistance between the wiring passing through the contact hole 112 and the impurity diffusion layer 101 is likely to be increased.
In addition, in order to completely remove the covering layer 107 on the side surfaces of the side walls 105, it may also be considered that the etching selectivity of Si3N4 to SiO2 can be made small to thus enhance anisotropy. In this case, there has been caused such a disadvantage that side surfaces of the SiO2 cap layer 104 covering the gate electrode 103 is etched and thus short-circuit between the wiring formed in the contact hole 112 and the gate electrode 103 would be caused.
Further, if overetching is carried out to remove completely the covering layer 107 between two gate electrodes 103, upper edges of the side walls 105 are also removed so that a part of the gate electrode 103 is exposed. As a result, the gate electrode 103 is short-circuited to a plug passing through the contact hole 112.
While, followings have arisen as problems in the BLC technique.
For example, if the etching selectivity of the silicon nitride to the silicon oxide cannot be enhanced when the silicon nitride film 132 is etched via the contact holes 134s, 134d formed in the interlayer insulating film 133, a surface of the buried insulating film 123 made of silicon oxide is etched to thus expose a part of the silicon substrate 121, as shown in FIG. 19. Therefore, since a metal plug formed in the contact holes 134s, 134d is also connected to the silicon substrate 121, the silicon substrate 121 and the metal plug are short-circuited so that a leakage current flows via such short-circuited portion.
The side wall 128 has been formed of silicon oxide in the above explanation. However, if the side wall 128 is formed of silicon nitride, the etching selectivity of the silicon nitride to the silicon substrate must be enhanced. More particularly, as shown on the left side in FIG. 20, the event that the low-impurity concentration regions 127s, 127d are etched upon vertical etching of the silicon nitride signifies that the low-impurity concentration regions 127s, 127d beneath the silicide layer 134s are made shallower and therefore resistances of the low-impurity concentration regions 127s, 127d are increased. In addition, as shown on the right side in FIG. 20, if an etching depth on the surface of the silicon substrate 121 is increased upon etching of the silicon nitride constituting the side wall 128a, a depletion layer extended from the impurity diffusion layer 130d cannot be stabilized, but also the silicide layer 134s protrudes from the low-impurity concentration regions 127s. As a result, a leakage current becomes easy to flow into the silicon substrate 121.
As described above, in the above prior art, there has been such a problem that the etching selectivity of the silicon nitride to the silicon oxide and the anisotropy have trade-off relations with each other.